Ethernet

Supported RMII PHY's:

• DP83848
• LAN8700
• RTL8201F

Features:

• IP (Internet Protocol, IPv4)
• ICMP (Internet Control Message Protocol)
• IGMP (Internet Group Management Protocol)
• DHCP, Zeroconf
• UDP (User Datagram Protocol)
• TCP (Transmission Control Protocol)

Applications:

• NTP client
• TFTP server
• HTTP server
• MDNS (Multicast DNS) responder

Example building the firmware for RTL8201F:

make -f Makefile.GD32 clean && make -f Makefile.GD32 ENET_PHY=RTL8201F

RTL8201F RMSR Timing Configuration (GD32F4xx only)

Purpose

The RTL8201F PHY contains an RMII Mode Setting Register (RMSR) located at page 7, register 16. This register controls several RMII interface options, including the PHY’s programmable RMII transmit timing offset and RMII receive timing offset.

In the RTL8201F datasheet these fields are defined as:

• Bits [11:8] — Rg_rmii_tx_offset : adjusts RMII TX interface timing
• Bits [7:4] — Rg_rmii_rx_offset : adjusts RMII RX interface timing

The default value for both fields is 1111b .

The datasheet states that RMII TX and RX timing are adjustable with a minimum resolution of approximately 2 ns. However, it also notes that modifying these values is generally not recommended, since the default configuration is intended to provide the optimum timing for most platforms.

RMSR Register Function

In RMII mode, the PHY and MAC exchange data relative to the shared 50 MHz REFCLK. The interface timing margin therefore depends on:

• setup time
• hold time
• internal PHY delay
• MAC sampling point
• PCB routing
• clock distribution

The RTL8201F exposes programmable delay/offset fields in RMSR so that the effective RMII timing can be adjusted if the default timing does not meet the platform’s timing requirements.

Functionally:

• RX timing offset adjusts the PHY-to-MAC RMII receive path.
• TX timing offset adjusts the MAC-to-PHY RMII transmit path.

The register also contains additional RMII configuration controls such as:

• RMII / MII mode selection
• RMII clock direction
• RXDV / CRS_DV behavior

Code Implementation

			
			#define RMSR_RX_TIMING_SHIFT 4
			#define RMSR_RX_TIMING_MASK  0xF0
			#define RMSR_TX_TIMING_SHIFT 8
			#define RMSR_TX_TIMING_MASK  0xF00
		
		

These constants match the RTL8201F bit allocation:

• RX timing field → bits [7:4]
• TX timing field → bits [11:8]

The function constructs a value containing only these two fields and writes it using:

WritePaged(0x7, PHY_REG_RMSR, phy_value, mask)

The WritePaged() helper performs the following operations:

1. Select PHY page 7
2. Read the current register value
3. Clear only the bits defined by the mask
4. Insert the new field values
5. Write the modified value back
6. Restore page 0

This is important because RMSR contains additional configuration bits beyond the timing offsets. The implementation modifies only the TX/RX offset fields while preserving the remaining register state.

This is the correct approach when applying timing compensation to RMSR.

Values Written by CustomizedTiming()

For GD32F4xx targets the following timing values are used:

• RMSR_RX_TIMING_VAL = 0x4
• RMSR_TX_TIMING_VAL
  • 0x2 for GD32F407
  • 0x1 for GD32F470
  • 0xF for other GD32F4xx targets

The resulting RMSR values written to the PHY are therefore:

• GD32F407
  phy_value = (0x4 << 4) | (0x2 << 8) = 0x0240
• GD32F470
  phy_value = (0x4 << 4) | (0x1 << 8) = 0x0140
• Other GD32F4xx
  phy_value = (0x4 << 4) | (0xF << 8) = 0x0F40

Because the datasheet specifies only the minimum adjustment resolution (2 ns) and does not provide a full transfer function for these codes, the values should be interpreted as timing tap selections rather than precise absolute delay values.